Riverlane is building the error correction stack
This will enable all quantum computers to become 'fault tolerant' by turning many noisy qubits into one or more logical qubits that perform reliable operations at scale.
Deltaflow.Decode, the foundation of our error correction stack, is the world's most powerful decoder technology. It predicts and corrects data errors on different qubit types at unprecedented speed, accuracy and efficiency. Performance metrics are detailed in our latest paper.
Deltaflow.Decode consists of two processor families:
- Decoder IP - Universal RTL (Firmware) that can be used with any FPGA vendor
- Decoder ASIC - Dedicated decoding chips offering greater speed and efficiency
Deltaflow.Decode processors are silicon-ready. We have optimised the underlying RTL implementation to be efficient whilst maintaining configurability and generality. They work with Riverlane's control system Deltaflow.Control and other third-party control systems.
Deltaflow.Decode Portfolio
Riverlane Processors
Decode IP
Software configurable, FPGA implementation of our fastest decode. By leveraging industry standards and best practices it can easily integrate with superconducting, ion trap and neutral atom qubits.
DD1 is Decode IP that supports a series of quantum error correction experiments with the surface code, including stability and quantum memory.
Explore DD1
Decode ASIC
Dedicated decoding semiconductor chips that work at high-speed, capacity, cost and power efficiency. Configurable with superconducting, ion trap and neutral atom qubits.
DD0A: The world's first decode ASIC. DD0A is a demonstration chip. DD1A will be produced in 2024.
