The biggest challenge in quantum computing is moving from noisy experimental devices to reliable, utility-scale machines. Central to this is real-time Quantum Error Correction (QEC): the technology that detects and corrects errors faster than they occur.
Over the past year, Riverlane has advanced QEC from theory to hardware-informed reality by integrating our Deltaflow QEC system with leading quantum architectures under the UK’s Quantum Missions Pilot.
In this post, we’ll highlight the work through two of our partnerships with Oxford Quantum Circuits (DECIDE) and Rigetti (HERMES), explaining how we demonstrated that real-time, integrated QEC is achievable.
DECIDE heralds accuracy improvements and HPC integration with OQC
Quantum computers are prone to relaxation errors, where a qubit changes state in an uncontrolled manner.
To combat this, researchers have employed erasure error conversion: specialised operations designed to detect if a qubit has relaxed without disturbing its quantum information. When an erasure check fires, it acts as a signal flare (or "herald"), alerting the decoder to the exact location of the error.
By identifying these erased qubits in real-time and resetting them back into the computational subspace, the system can transform a fatal, unknown relaxation event into a manageable “erasure” error. This is because the knowledge of these errors can be leveraged by the decoder, leading to improved accuracy and better logical error suppression.
However, simulating erasure can be computationally expensive, and standard simulators tend to ignore it. At Riverlane, we developed a simulator (deltakit-stim) that can model erasure errors as standard computational errors. By doing so, we can simulate very large quantum error correction circuits that contain erasure errors in a fast and efficient manner.
During the project, we extended the capabilities of our simulator to model Oxford Quantum Circuits’ dual-rail qubits. We introduced the feature that allowed us to perform erasure checks throughout the computation, letting us check for erasure as often as needed without directly measuring the qubits.
“By having multiple erasure checks, we can address the exact location of a leakage error during the computation. This is very valuable for error correction as it enables better error suppression,” Gianluca Aiello, staff quantum scientist at Riverlane, explained.
Using OQC's noise model and by mapping leakage errors to standard computational errors, we leveraged Stim to develop our high-performance deltakit-stim simulator to efficiently model QEC codes with erasure checks. Our simulations discovered that more frequent checks substantially improved circuit performance, in some noise models nearly doubling the Lambda (Λ) value.
Lambda is a key performance metric for all quantum computers. It measures how effectively logical errors are suppressed as a QEC code scales. Higher Lambda means more error suppression and a lower qubit overhead. In other words, you can run more error-free quantum operations (QuOps) using the same quantum hardware.
However, there’s a trade-off: imperfect checks can add noise, so hardware designers must balance the erasure check frequency against circuit reliability. To address this, we built a resource estimator that lets hardware teams calculate exactly how many extra erasure checks is optimal.
This project delivered a fast leakage simulator (le-stim) that can model "heralded" errors (flags that effectively say "this qubit is broken"), showing that more frequent checks (e.g., 2 or 4 per round) lead to much better error suppression.
This means we can build larger, more reliable quantum computers, where relaxation errors no longer represent an impenetrable barrier to scaling up and effectively tackling a range of critical real-world problems
We also successfully deployed OQC's Qblox control system, connected it to our Deltaflow real-time QEC system, and integrated it with an HPC cluster, which is a crucial step for real-world deployments that require the integration of classical supercomputers and quantum computers. You can read more about our wider work with Qblox and OQC here.
The next step is the hardware deployment of these erasure-aware decoding capabilities into the Deltaflow system to handle real-world leakage on OQC hardware.
“Real-time quantum error correction is the critical bridge between today’s devices and tomorrow’s utility-scale quantum computers. Through our collaboration with Riverlane on DECIDE, we’ve shown that integrating hardware-aware error detection with high-performance classical infrastructure can meaningfully improve system performance. This kind of tightly coupled innovation across the stack is exactly what’s needed to unlock scalable quantum computing,” said Simon Phillips, CTO at OQC.
Figure 1: We applied erasure-aware simulations and decoded pipeline to OQC’s predicted noise model, showing that Lambda (Λ) increases with the erasure-check granularity and more heralds per cycle reduce the logical error rate at fixed distance.
HERMES helps break the backlog problem with Rigetti
The backlog problem is a major challenge in quantum computing. As quantum processors (QPUs) become faster and more complex, they will generate error data at a staggering rate: of the order of terabytes per second. If you can’t decode and fix those errors in real-time, the quantum computation eventually grinds to a halt.
During this project, we addressed this challenge, integrating Riverlane’s Deltaflow 2 QEC system with Rigetti’s 36-qubit AnkaaTM-class system hosted at the NQCC to perform streaming decoding.
Here, the decoder receives a constant stream of data from the qubits, calculates the most likely errors, and must stay perfectly in sync with the quantum control system, all while the experiment is still running.
Using a repetition code, the team successfully ran an experiment consisting of more than 10,000 measurement rounds. We saw no exponential slowdown in computing time, meaning the backlog problem was successfully avoided.
This is a significant milestone because it demonstrates that Deltaflow can keep pace with the QPU’s operations indefinitely. We aren't just decoding faster; we are decoding in a way that is truly scalable. You can also read more about latency and our most recent results comparing Deltaflow to Google’s systems here.
Beyond the hardware integration, HERMES also tackled context-optimised calibration. By calibrating operations on the device using methods designed to find optimal performance within the specific context of the circuit in which they were to be executed, the logical error probability after decoding was found to be substantially reduced.
This data provides Rigetti and the wider ecosystem with a clear, data-driven roadmap, indicating which physical errors need to be prioritised to reach the next tier of quantum performance.
"This result is very exciting as it is the first time we have demonstrate an integration between physical qubits and a dedicated QEC system. We were particularly excited to demonstrate streaming decoding as it is an important aspect of scalable fault tolerant quantum computation," Laura Caune, staff quantum scientist at Riverlane, explained.
“Scaling quantum computing systems towards utility-scale requires that QEC is effectively integrated with quantum computing control systems, and that’s exactly what we’ve achieved with this project. Demonstrating that we can decode quantum errors in real-time on real quantum hardware with a high number of error detection rounds addresses a crucial bottleneck towards achieving fault-tolerant quantum computing,” said David Rivas, Rigetti CTO.
Conclusion: From theory to national capability
The results from DECIDE and HERMES have delivered three critical insights on the road to utility-scale computing:
- QEC must be hardware-informed: There is no "one-size-fits-all" QEC integration. Success depends on building QEC systems that understand the specific profiles of the underlying qubits.
- The backlog problem is solvable: We have demonstrated that classical infrastructure can keep pace with high-speed QPUs, decoding error data in real-time without the system grinding to a halt.
- Integration is key: The future of quantum computing is hybrid. By successfully connecting QEC layers with HPC clusters and commercial control systems, we are building a deployable national capability.
As we move into the next phase of work, Riverlane remains committed to creating the real-time QEC system across the quantum ecosystem to enable our partners to reach utility-scale quantum computing faster.
If you want to find out more about our work with our partners across the quantum ecosystem, click here.